National University of Sciences and Technology
Home | Back
EC-825 Advanced Digital System Design
Campus College of E&ME
Programs PG
Session Fall Semester 2016
Course Title Advanced Digital System Design
Course Code EC-825
Credit Hours 3-0
Pre-Requisutes Digital Logic Design, Computer Architecture, Signals and Systems.
Course Objectives This course is designed to introduce engineers and designers advanced digital design concepts. The students are taught different steps in the design flow of VLSI IC circuit designing using Verilog. They will be exposed to converting floating-point algorithms to Fixed point format and then optimally designing the HW to implement the algorithm. After successful completion of the course a student will able to design digital systems using Register Transfer Level Verilog.
Detail Content Objective:
This course is designed to introduce engineers and designers advanced digital design concepts. The students are taught different steps in the design flow of VLSI IC circuit designing using Verilog. They will be exposed to converting floating-point algorithms to Fixed point format and then optimally designing the HW to implement the algorithm. After successful completion of the course a student will able to design digital systems using Register Transfer Level Verilog.

Course Outcomes
After this course have an in-depth knowledge of digital integrated circuit hardware design. The emphasis is on FPGA technology, but most of the design techniques can also be applied to ASIC devices. The student should be familiar with the latest state-of-the-art system on chip (SoC) design methodologies, including high-level synthesis and partial run-time reconfiguration. Students should be able to learn the benefits and drawbacks of the various design methods for solving a problem. Through practical assignments, experience will be achieved from both using tools as well as designing their own system.

Topic
  • High-level digital design methodology using Verilog, Design, Implementation, and Verification.
  • Application requiring HW implementation, Floating-Point to Fixed-Point Conversion.
  • Architectures for Basic Building Blocks, Adder, Compression Trees, and Multipliers.
  • Transformation for high speed using pipelining, retiming, and parallel processing.
  • Dedicated Fully Parallel Architecture.
  • Time shared Architecture.
  • Hardwired State Machine based Design.
  • Micro Program State Machine based Design.
  • FPGA-based design and logic synthesis.
Text/Ref Books 1. Digital Design of Signal Processing Systems by Shoab A. Khan (2011),John Wiley & Sons References:
1. Verilog HDL-A guide to digital design and synthesis by Samir Palnitkar, Prentice Hall Publisher.
2. Advanced Digital Design with Verilog HDL by Michael D. Ciletti, Prentice Hall Pulisher.

Evaluation Methods: Quizzes: 4-6 (8%)
Assignments and project: 4-6 (6%).
Sessional exams 2: (18% + 18%).
Final exam 1: (50%).
Time Schedule Theory: - Three lectures of one hour each per week.
Faculty/Resource Person